This year, for the first time I made it to the International Consumer Electronics Show (CES) in Las Vegas. To say it is an endurance test is putting it mildly – close to 150,000 attendees predicted and ~5,000 media/analysts, so we (there’s two of us from Chipworks) spend more time standing in line than actually seeing the show. Be that as it may, Tuesday morning we went to one of…
Siliconica
TI Debuts 28-nm OMAP 5 Processor at CES
This year, for the first time I made it to the International Consumer Electronics Show (CES) in Las Vegas. To say it is an endurance test is putting it mildly – close to 150,000 attendees predicted and ~5,000 media/analysts, so we (there’s two of us from Chipworks) spend more time standing in line than actually seeing the show. Be that as it may, Tuesday morning we went to one of…
TI Debuts 28-nm OMAP 5 Processor at CES
This year, for the first time I made it to the International Consumer Electronics Show (CES) in Las Vegas. To say it is an endurance test is putting it mildly – close to 150,000 attendees predicted and ~5,000 media/analysts, so we (there’s two of us from Chipworks) spend more time standing in line than actually seeing the show. Be that as it may, Tuesday morning we went to one of…
IEDM 2011: IBM displays via-middle TSV process for die stacking
A few days after IBM and Micron publicized their hybrid memory cube, IBM gave their TSV paper at IEDM on the Monday afternoon (paper 7.1). Entitled "3D Copper TSV Integration, Testing and Reliability," they described a node-agnostic through-silicon via (TSV) technology which takes a via-middle configuration, making contact to the upper metal (fat-wire) layers in the device structure. By "node-agnostic" they mean that they proved the concept in devices fabbed…
IEDM 2011: IBM displays via-middle TSV process for die stacking
A few days after IBM and Micron publicized their hybrid memory cube, IBM gave their TSV paper at IEDM on the Monday afternoon (paper 7.1). Entitled "3D Copper TSV Integration, Testing and Reliability," they described a node-agnostic through-silicon via (TSV) technology which takes a via-middle configuration, making contact to the upper metal (fat-wire) layers in the device structure. By "node-agnostic" they mean that they proved the concept in devices fabbed…
IEDM 2011: IBM displays via-middle TSV process for die stacking
A few days after IBM and Micron publicized their hybrid memory cube, IBM gave their TSV paper at IEDM on the Monday afternoon (paper 7.1). Entitled "3D Copper TSV Integration, Testing and Reliability," they described a node-agnostic through-silicon via (TSV) technology which takes a via-middle configuration, making contact to the upper metal (fat-wire) layers in the device structure. By "node-agnostic" they mean that they proved the concept in devices fabbed…
IEDM 2011 Preview
Next week the researchers and practitioners of the electron device world will be gathering in Washington D.C. for the 2011 IEEE International Electron Devices Meeting. To quote the conference web front page, “IEDM is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS…
IEDM 2011 Preview
Next week the researchers and practitioners of the electron device world will be gathering in Washington D.C. for the 2011 IEEE International Electron Devices Meeting. To quote the conference web front page, “IEDM is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS…
Intel clarifies 32nm NMOS stress mechanism at IEDM 2011
I was browsing through the advance program for the upcoming IEDM conference when, almost at the end, I came across paper number 34.4, "Modeling of NMOS Performance Gains from Edge Dislocation Stress," by Weber et al. of Intel. According to the abstract: "Simulations show stress from edge dislocations introduced by solid phase epitaxial regrowth increases as gate pitch is scaled, reaching over 1GPa. This makes edge dislocations attractive, as stress…
Intel clarifies 32nm NMOS stress mechanism at IEDM 2011
I was browsing through the advance program for the upcoming IEDM conference when, almost at the end, I came across paper number 34.4, "Modeling of NMOS Performance Gains from Edge Dislocation Stress," by Weber et al. of Intel. According to the abstract: "Simulations show stress from edge dislocations introduced by solid phase epitaxial regrowth increases as gate pitch is scaled, reaching over 1GPa. This makes edge dislocations attractive, as stress…
