Efabless Corporation today announced its AI Generated Open-Source Silicon Design Challenge which provides a hands-on opportunity to experience how simple it can be to use AI to create and tapeout chip designs in days or even hours. The mission of the design challenge is two-fold. First, it will demonstrate the potential of Generative AI to accelerate chip innovation by simplifying design and doing it faster and for less cost. Second, it will seed a cohort of interested parties who will learn from their respective experiences, amplified by the transparency that open source designs provide to successes and lessons learned.
Generative AI offers the potential to revolutionize chip design by automating many of the time-consuming tasks involved in the process. In this challenge, participants will use Generative AI (e.g., chatGPT, Bard or similar) to generate Verilog from natural language prompts. The designs will then be implemented using the Efabless chipIgnite platform, which includes an SoC template (Caravel) providing rapid chip-level integration, and an open-source RTL-to-GDS digital design flow (OpenLane).
We are intending to manufacture at least three winning designs. The winning designers will receive packaged parts of their designs and evaluation boards – a value of $9,750. Winners will be chosen by a panel of industry-respected judges according to criteria listed on the challenge landing page. The first 25 participants with qualifying designs will receive an evaluation board and one of the winning AI generated chips upon completion of the fabrication.
“We are excited to launch this challenge and to see the designs the community comes up with,” said Mike Wishart, CEO of Efabless. “Generative AI has the potential to transform chip design and open source makes the learnings available to all. We believe that the challenge is an exciting and important first step for both Efabless and for our community.”
