DAVID LAMMERS and PETE SINGER, Semiconductor Digest
When Intel CEO Pat Gelsinger announced in July of last year that Intel intended to roll out four transistor technology generations in five years, achieving performance-per-Watt parity with the leading foundries in 2024 and leadership in 2025, many scoffed. How could the company that had gone from unchallenged leader to struggling follower, the sceptics argued, make such a transformation?
However, leaders of Intel’s Logic Technology Development (LTD) organization recently have affirmed that Intel is meeting its development benchmarks for the 4nm, 3nm, 20Å (Angstrom), and 18Å nodes. Moreover, Sanjay Natarajan, LTD’s co-general manager, said Intel would be ready with its 18Å node by the end of 2024, one quarter earlier than previously announced.
In a press briefing, Natarajan said Intel benchmarks its progress in detail. “Indicators for all of these technology nodes are all very positive,” he said. “We are on or ahead of our milestones for each of them.”
As the Intel managers were speaking to reporters, Scotten Jones, an industry analyst who closely follows the progress of Intel and foundries TSMC and Samsung in logic technology, was presenting at the SEMI Industry Strategy Symposium (ISS). After detailing Intel’s failures during the 14nm and 10nm nodes, Jones said there are indicators Intel is keeping on schedule with its “Intel Accelerated” plans.
“I think Intel really does seem to have made a big turnaround in their ability to develop and introduce these technologies,” Jones said. “If they execute on this accelerated roadmap, which they appear to be doing, they could be the performance leader in 2025. I think TSMC might still be the density leader, while Intel could be the performance leader. Intel is claiming they’ll be a performance leader in 2025. I think they have a good shot of doing that.”
Jones, who runs a consultancy, IC Knowledge LLC (Georgetown, Mass.), focused on modeling semiconductor costs, noted that performance is Intel’s primary concern for its microprocessor products, while TSMC puts more emphasis on density and power. Starting at the 20Å node, Intel plans to introduce its version of the Gate All Around transistor architecture, RibbonFET, as well as a power delivery architecture on the backside of the wafer, called PowerVia. Jones said by putting four thick metal layers on the underside, it may help solve the IR drop challenges which are so critical for high-performance devices.
Click here to read the full article in Semiconductor Digest magazine.
