“Moore’s Law” will inevitably come to a screeching halt, says Monozukuri CEO and Founder, Anna Fontanelli. Integrating chiplet, package and integrated circuit (IC) systems through a seamless IC/packaging co-design methodology re-opens the path to next gen IC innovation.
Ms. Fontanelli shared her prediction and resolution with semiconductor leaders recently at SemIsrael, addressing why a broad swath of the world’s population should pay attention to the growing importance of advanced packaging and 3D integration.
“With integrated circuits continuously shrinking and the continuous evolution of technological processes, Moore’s Law is entering a bottleneck,” Ms. Fontanelli pointed out. “At present, 3D integration technology is a new hope to solve this dilemma.”
Shrinking transistors below a 1-nanometer node gets closer to the technology’s limit. To further scale IC functionality means moving “off chip” to vertical IC integration. This, Ms. Fontanelli explains, is the most practical way – perhaps the only way – to increase design complexity, reduce time-to-market and lower per unit costs. Certainly, it’s more economically viable than extreme miniaturization, she claims.
Key to this new direction is that stand-alone ICs … sensors, memories, microprocessors, and RF … can now be integrated into a single unit on configurable silicon substrates and advanced packaging technologies.
Stacking chips horizontally and vertically makes possible another step up in performance and expanding the Moore’s law. However, the move from traditional planar design to 3D integration brings many challenges.
New EDA tools, methodologies and flows must be developed to automate IC, package and ultimately the entire electronic system design process, while at the same time reducing design time, and enabling greater integration.
Ms. Fontanelli then introduced Monozukuri’s GENIO. GENIO was the first integrated IC/Packaging EDA tool on the market. It facilitates the widespread use of 3D-ICs, enabling the design of complex heterogeneous configurations. It’s advanced co-design environment integrates with traditional package and IC design tools through a standard format that streamlines the design flow.
GENIO features system architecture exploration, what-if analysis, 3D interconnect management, I/O planning and optimization, integrated within all existing EDA implementation platforms. It’s optimization algorithms tame the computational complexity of 3D designs. It supports all system architectures (2D, 2.5D, 3D configurations), all assembly styles (wire-bonding, flip-chip, and mixed) and all design flows (die-driven, package-driven, a mixture of top-down & bottom-up).