Lattice Semiconductor (NASDAQ: LSCC), the low power programmable leader, today introduced the CrossLinkPlus™ FPGA family for MIPI D-PHY based embedded vision systems. CrossLinkPlus devices are innovative, low power FPGAs featuring integrated flash memory, a hardened MIPI D-PHY and high-speed I/Os for instant-on panel display performance, and flexible on-device programming capabilities. Additionally, Lattice provides ready-to-use IPs and reference designs to accelerate implementation of enhanced sensor and display bridging, aggregation, and splitting functionality, a common requirement for industrial, automotive, computing, and consumer applications.
Developers want to enhance the user experience by adding multiple image sensors and/or displays to embedded vision systems, while also meeting system cost and power budgets. Lattice addresses this need with CrossLinkPlus FPGAs: small (3.5 x 3.5 mm), low power (< 300 µW) devices specifically optimized for embedded vision applications with features like a hardened MIPI D-PHY, broad high-speed I/O support for interfaces like OpenLDI and RGB, and on-chip non-volatile flash memory. CrossLinkPlus utilizes its on-chip flash to support instant-on (minimizing visual artifacts that detract from the user experience) and flexible device reprogramming in the field.
“The use of MIPI D-PHY in applications ranging from industrial control equipment displays to AI security cameras is booming as OEMs look to capitalize on the economies of scale driven by the MIPI ecosystem,” said Peiju Chiang, Product Marketing Manager, Lattice Semiconductor. “Lattice’s new CrossLinkPlus FPGAs combine the flexible programmability and speedy parallel processing of FPGAs with vision-specific hardware, software, pre-verified IPs and reference designs. This lets OEMs devote more time to building innovative applications and less time enabling standard functions that don’t offer any competitive differentiation.”
Key features of the CrossLinkPlus family of FPGAs include:
· On-device reprogrammable flash memory to enable instant-on (< 10 ms)
· Hardened, pre-verified MIPI D-PHY interface supporting speeds up to 6 Gbps per port
· Broad support for high-speed I/O interfaces such as LVDS, SLVS and subLVDS
· Comprehensive IP library, including MIPI CSI-2, MIPI DSI, OpenLDI transmitters and receivers. These IPs are compatible with other Lattice FPGAs for easy design portability.
· Fully compatible with the Lattice Diamond® design software tool flow, from synthesis and design capture through implementation, verification, and programming
· Power consumption as low as 300 µW (standby) or 5 mW (operating)
Originally scheduled to begin sampling in Q4 2019, Lattice has already provided samples of its CrossLinkPlus FPGAs to customers for use in industrial and automotive applications. For more information about the CrossLinkPlus FPGA family, please visit http://www.latticesemi.com/en/Products/FPGAandCPLD/CrossLinkPlus.
