By Pete Singer, Editor-in-Chief
On Monday, in advance of SEMICON West, imec hosted its annual International Technology Forum (ITF). Luc Van den hove, president and CEO of imec, presented his view of a 20 year technology roadmap which he said is even more aggressive than what the industry has achieved over the last decades. “We will leverage our core semiconductor expertise to realize deep-tech innovations by co-innovating at the semiconductor technology level, the system and application levels, and by leveraging expertise from many domains such as material science, biomedical, pharma, AI, and others,” Van den hove said.
Building flourishing deep-tech ecosystems must become a priority to meet the challenges of the 21st century, including those in the medical field, addressing the food shortages, tacking climate change and air pollution, finding solutions for sustainable mobility. “All of these challenges require us to develop real deep tech technology solutions,” he said. “All of these challenges will require massive data handling, and will therefore require making our technologies more and more performant.”
The semiconductor industry has long relied on traditional Dennard’s-based scaling, which simultaneously provided increased performance and increased density at a reduced power and a reduced cost. “This one-dimensional version of the roadmap may not be sufficient anymore for the future,” said Van den hove. “We will have to tune our devices for specific applications.”
Traditional scaling is hitting multiple walls in terms of power, performance, scaling and cost. “Just the lithography based shrinking is getting harder,” Van den hove said. “It’s not stopping, but it’s getting harder and harder. The performance improvement that we are used to for single transistors from node to node has been slowing down. This is why we had to go to massive parallelization.”
System performance becomes increasingly dominated by data path limitations between the core processor and the memory, which creates data handling limitations, particularly in AI applications. “This is what we refer to as the Memory Wall. Memory peak bandwidth cannot keep up with processor peak throughput,” Van den hove said.
Another wall is the Power Wall. “It becomes harder and harder to get all the power into our chip, but also to extract the heat out of each chip. Therefore, we need new cooling techniques,” he said.
Cost is also exploding (the Cost Wall), which needs to be compensated by the complexity increase.
“Traditional scaling clearly is hitting many of these walls, and we will have to develop technology solutions actually to tear down those walls in order to enable the continuation of Moore’s Law,” Van den hove said.
For this wall tear-down, a multitude of approaches are needed, including dimensional shrinking, the development of new switches/transistors, increased use of the third dimension, and a system level approach to design optimization.
High NA EUV needed in 3 years
Imec hosted some of the earliest work on EUV, and Van den hove said the lithography roadmap experienced a “phenomenal boost” recently with the introduction of EUV into high volume manufacturing. “This happened at the five nanometer node. It was much harder than originally expected. It took much longer, but thanks to the phenomenal dedication and commitment of companies such as ASML and Zeiss,” he said. “The current version flavor of EUV we believe will be extendable down to the two nanometer generation or maybe even a node further, but to go beyond that, we will need a next version of EUV.” This will require bigger lenses and new system platforms to be developed. The optics must adhere to phenomenal specifications, 20 picometer accuracy over for a lens with a diameter of one meter. “If we extrapolate this to the size of the earth, it means that we would have to Polish the earth with an accuracy of the thickness of a human hair. This is unbelievable, mind boggling,” said Van den Hove. “We expect that the first machines will be ready next year.”
Introduction of high NA EUV will also come many challenges on the process side. “In order to address those in the proactive way, we’re setting up together with ASML, a joint high NA lab built around the first prototype machine, which will be interfaced to a TEL track and surrounded with the most advanced metrology capabilities. We are doing that because the challenge to introduce high NA EUV in a timely fashion will be tremendous,” Van den hove said. “It took us about 10 years to go from the first EUV scanner to insertion into high volume manufacturing. For high NA, we will have much less time, only three years. In order to derisk that introduction in manufacturing, we are setting up a very intensive program in order to develop all the key enabling building blocks, such as the mask technology and the materials using wet or dry UV resist, metrology and optics characterization.”
Device innovations
Van den hove described several proposed innovations for disruptive transistor architectures in order to enable further scaling, including the gate-all-around devise built up of a stack of nanosheets, and a new transistor concept called the forksheet device in which the N and the P channel transistors are moved closer together. “This forksheet device, we see as an extension of the standard nano sheet concept, and we believe it will be introduced around the equivalent of the one nanometer generation,” Van den hove said. He also described an option where the N and the P channel transistors are stacked on top of each other, called a complimentary FET (CFET) device.
“It’s clear that you can realize another very important step in cell size shrinking, but obviously at the expense of much more complex contacting schemes to contact the source and drain areas. But we believe that we have found developed integration schemes that would enable such transistor by optimizing the epi processes, patterning processes, and leveraging also very sophisticated deposition processes to enable the contacting structures,” said Van den hove.
Other innovations include reducing the thickness of the silicon channels to reduce channel length. This could be enabled through the use of new materials, replacing the silicon with 2D materials, atomically flat mono layers, for example, tungsten or molybdenum sulfides or selenides. “We’ve recently demonstrated the first versions of devices fabricated using 300 millimeter equipment,” he said.
20 year roadmap
Van den hove said a combination of continued dimensional scaling, new transistor architectures, new materials introduction, combined with innovative interconnect architectures (buried power rails) will be the secret to success. “We believe that we can propose a roadmap for the next eight to 10 generations — with an introductory pace of two to two-and-a-half year cadence — would bring us a roadmap for the next 20 years,” he said.