Alchip Technologies is putting teeth into its role as a founding member of TSMC’s 3DFabric Alliance by enhancing its 3nm process technology and advanced packaging capabilities.
The company supports the foundry initiative, announced in late October, seeing it as a market driver that will deliver Alchip’s most advanced high-performance computing ASIC technology to leading edge customer applications.
TSMC’s 3DFabric is a comprehensive family of 3D silicon stacking and advanced packaging technologies that unleash customer’s innovation in system level approach. It consists of TSMC’s frontend technologies or TSMC-SoIC (System on Integrated Chips), dedicated fabs for 3D stacked dies’ assembling and testing, and TSMC 3DFabric’s backend technologies include CoWoS and InFO family of packaging technologies.
The TSMC 3DFabric Alliance is the latest addition to TSMC’s Open Innovation Platform (OIP). The new alliance partners have early access to TSMC’s 3DFabric technologies, enabling them to develop and optimize their solutions in parallel with TSMC. This gives customers early availability to EDA, IP, memory, outsourced semiconductor assembly and test (OSAT), substrate, and testing.
“As a high-performance computing ASIC leader, Alchip’s participation in the TSMC 3DFabric Alliance is an imperative,” said Johnny Shen, president and CEO of Alchip Technologies. “This new initiative solidifies TSMC’s semiconductor leadership by providing strategic opportunities for leading-edge, high-performance ASIC companies to extend their most advanced packaging capabilities to innovative technology customers.”
Alchip has been taking 3nm customer ASIC designs and tapeout its first test chip in January 2023. It became the first dedicated high-performance ASIC company to announce total design and production ecosystem readiness targeting TSMC’s latest N3E process technology.
On the advanced packaging front, Alchip is fine tuning its industry leading chip-on-safer-on-substrate (CoWoS) packaging capability. CoWoS improves overall chip interconnect density and performance and is critical to nearly every high-performance computing (HPC) ASIC.
CoWoS is a 2.5D wafer-level multi-chip packaging technology that incorporates side-by-side die on a silicon interposer. Micro-bumps bond individual chips to a silicon interposer, forming a chip-on-wafer. Packaging is completed by bonding to a package substrate.
CoWoS chiplet sets include a high-performance system-on-a-chip (SoC) and a high-performance memory (HBM3 or HBM2E) block. Alchip’s CoWoS service covers all CoWoS package types such as CoWoS-S, CoWoS-R and CoWoS-L.