Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced that the Lattice Diamond and Lattice Radiant FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. In addition to tool access, the partnership also provides DARPA organizations with access to a selection of Lattice’s most popular soft IP cores and technical support to accelerate technology innovation for DARPA programs and foster the use of Lattice low-power FPGAs in DARPA-designed applications. The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.
DARPA launched the DARPA Toolbox initiative in 2020 to help remove potential roadblocks for resource-constrained researchers and increase the pace of innovation. Through the initiative, researchers receive greater access to Lattice software tools and technologies via the Lattice/DARPA partnership. The initiative exposes Lattice technologies to more users and increases the likelihood those technologies will be used in future production systems.
“Partnering with technology innovators like Lattice through our DARPA Toolbox initiative serves to streamline access for our organizations to cutting-edge technologies,” said Serge Leef, the Microsystems Technology Office (MTO) program manager at DARPA and leader of the DARPA Toolbox initiative. “Lattice’s portfolio of FPGA design tools and soft IP cores offer a compelling platform for our researchers to consider when implementing applications requiring artificial intelligence at the Edge, 5G communications, and/or automation.”
“Lattice has a 35 year heritage in developing highly reliable and low-power programmable logic solutions for use in communications, computing, industrial, automotive, and consumer applications. Our partnership with DARPA extends the reach of our low-power Lattice Nexus platforms to the DARPA ecosystem,” said Jim Tavacoli, Senior Director of Product Marketing, Lattice Semiconductor. “With the introduction of the Lattice Nexus platform, Lattice became the first low-power FPGA vendor to implement its devices using a 28nm FD-SOI development platform, enabling Lattice Nexus FPGAs to provide up to a 75 percent reduction in power consumption and a Soft Error Rate (SER) up to 100 times lower than similar FPGAs in their class.”