Cadence Design Systems, Inc. today announced the new Cadence Certus Closure Solution to address growing chip-level design size and complexity challenges. The Cadence Certus Closure Solution environment automates and accelerates the complete design closure cycle from weeks to overnight—from signoff optimization through routing, static timing analysis (STA) and extraction. The solution supports the largest chip design projects with unlimited capacity while substantially improving productivity by up to 10X versus current methodologies and flows.
The Cadence Certus Closure Solution eases the design signoff closure bottlenecks and complexities that come with developing today’s emerging applications like hyperscale computing, 5G communications, mobile, automotive and networking. Prior to the introduction of the Cadence Certus Closure Solution, a full-chip closure flow involved manual, tedious processes from full chip assembly, static timing analysis, and optimization and signoff with 100s of views, taking designers months to converge. The new solution provides a fully automated environment that is massively distributed for superior optimization and signoff. This allows concurrent, full-chip optimization through an engine shared with Cadence’s Innovus™Implementation System and the Tempus™ Timing Signoff Solution, eliminating iterative loops with block owners while enabling designers to make quick optimization and signoff decisions. Furthermore, in conjunction with the Cadence Cerebrus™ Intelligent Chip Explorer, designers can experience additional productivity improvements from block-level to full-chip signoff closure.
The Cadence Certus Closure Solution provides customers with the following benefits:
- Innovative scalable architecture: The Cadence Certus Closure Solution’s distributed hierarchical optimization and signoff architecture is ideal for cloud-execution and is operational in both cloud and internal data center environments
- Incremental signoff: Provides flexible restore and replacement of only the changed portions of the design, further accelerating final signoff
- Improved engineering productivity: Fully automated flow reduces the need for multiple, lengthy iterations across multiple teams, providing faster time-to-market
- SmartHub interface: Enhanced interactive GUI allows cross-probing for detailed timing debug to drive last-mile design closure
- 3D-IC design efficiencies: Tightly integrated with the Cadence Integrity 3D-IC Solution, it allows users to close inter-die paths across heterogenous process dies
“Today’s design teams often spend five to seven days per iteration to meet chip-level signoff timing and power requirements, and previous methodologies failed to deliver the team collaboration and user experience needed for efficient design closure,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “We are intensely in tune with the needs of the design community, and with the release of the new Cadence Certus Closure Solution, we’re offering our customers a novel environment for chip-level optimization and signoff that delivers exceptional PPA results within a matter of hours. With this new Cadence solution, we’re empowering customers to achieve productivity goals and deliver products to market faster.”