SmartDV™ Technologies today announced NSITEXE licensed its TileLink VIP to ensure complete verification of its high-efficiency and high-quality semiconductor IP adaptable to various applications using the RISC-V architecture.
NSITEXE selected SmartDV because it is the only VIP solutions provider to offer a smart way to verify the TileLink fabric and reduce verification time. SmartDV’s VIP verifies the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based or alternative architecture system-on-chip (SoC) designs.
According to Hideki Sugimoto, chief technology officer (CTO) at NSITEXE, Choosing SmartDV’s TileLink VIP was a smart decision for its power-efficient data flow processor (DFP) IP used in in-vehicle, industrial applications, and other market segments. “It accelerated TileLink implementation and verification through faster testbench development.”
“NSITEXE’s mission to contribute to the evolution of next-generation semiconductor technology through its semiconductor IP products neatly aligns with our mission and goals,” remarks Deepak Kumar Tala, SmartDV’s managing director. “We pride ourselves on evolving next-generation SoC designs with our sizable portfolio of standard and custom protocol VIP fully compliant with standard protocol specifications. Users like NSITEXE can verify and debug their designs quickly, easily and more effectively.”
SmartDV will exhibit at the RISC-V Summit today (Tuesday, December 10) from 11:30 a.m. until 7 p.m. and Wednesday, December 11, from 11:30 a.m. until 4 p.m. at the San Jose Convention Center, San Jose, Calif. It will highlight the TileLink VIP and its Verilator VIP, and demonstration its Smart ViPDebug™, a visual protocol debugger that reduces debug time. Attendees can schedule demos or meetings at demo@smart-dv.com.