Verific Design Automation, a provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms, today announced Rapid Silicon, a provider of AI-enabled application-specific FPGAs based on open-source technology, is the newest licensee of its Parser Platform.
Rapid Silicon is quickly building a reputation as the leader of domain-specific, power-, performance- and area-optimized FPGAs for diverse target applications using an open-source methodology and proprietary AI technology to enable a fast and seamless design-to-silicon experience. It will use the Verific Parser Platform including SystemVerilog, VHDL and elaborators for both to serve as the front end to Rapid Silicon’s integrated design environment.
“Verific’s parser platform has the well-earned status of industry standard,” says Pierre-Emmanuel Gaillardon, CTO of Rapid Silicon. “All of the accolades about Verific are valid, a result of its robust, quality software through years of development and user experience and exceptional customer support. It’s a pleasure to work with Verific.”
“Rapid Silicon’s aims to set the standard for FPGAs and FPGA SoCs by building the largest independent AI-enabled FPGA company,” adds Michiel Ligthart, Verific’s president and COO. “We take pride in playing a role in helping to enable a fast and seamless design-to-silicon experience.”
Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are in production and development flows at semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to hardware emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compiles on all 32- and 64-bit Unix, Linux, Mac OS and Windows operating systems.