Synopsys Accelerates Cloud Computing SoC Designs with New Die-to-Die PHY IP in Advanced 7nm FinFET Process

Shannon Davis

5 years ago

Synopsys, Inc. (Nasdaq: SNPS) today announced its DesignWare® Die-to-Die PHY IP for ultra- and extra-short reach connectivity in multi-chip modules (MCM) for hyperscale data center, AI, and networking designs. The DesignWare Die-to-Die PHY IP supports NRZ and PAM-4 signaling from 2.5G to 112G data rates, delivering maximum throughput per die edge for large MCM designs. To improve SoC yield, the Die-to-Die PHY allows for partitioning of large dies into smaller dies while offering trade-offs for power, bandwidth per beachfront, latency, and reach.

Synopsys, Inc. (Nasdaq: SNPS) today announced its DesignWare^® Die-to-Die PHY IP for ultra- and extra-short reach connectivity in multi-chip modules (MCM) for hyperscale data center, AI, and networking designs. The DesignWare Die-to-Die PHY IP supports NRZ and PAM-4 signaling from 2.5G to 112G data rates, delivering maximum throughput per die edge for large MCM designs. To improve SoC yield, the Die-to-Die PHY allows for partitioning of large dies into smaller dies while offering trade-offs for power, bandwidth per beachfront, latency, and reach. The DesignWare Die-to-Die PHY is the latest addition to Synopsys’ comprehensive cloud computing IP solution consisting of silicon-proven 112G/56G Ethernet HBM2/2E, DDR5/4, and PCI Express 5.0 controller, PHY, and verification IP.

Synopsys provides designers with a comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models, and crosstalk analysis for fast integration of the DesignWare Die-to-Die PHY into SoCs. The half-duplex transmitter and receiver in a X16 lane configuration delivers 1.8 terabit-per-second per millimeter unidirectional bandwidth for high throughput die-to-die connectivity. To meet the power requirements of SoCs in advanced FinFET processes, the Die-to-Die PHY delivers less than one picojoule per bit (pJ/bit) for ultra-low-power die-to-die and die-to-optical engine connectivity. The DesignWare Die-to-Die PHY IP is compliant with the OIF CEI-112G and CEI-56G standards for ultra-short reach (USR) and extra-short reach (XSR) links.

“Advanced SoCs for high-end data center and networking applications are reaching maximum reticle size limits, requiring designers to partition the SoC into smaller modular dies,” said John Koeter, vice president of marketing for IP at Synopsys. “The DesignWare Die-to-Die PHY IP with leading power, performance, and area is enabling our customers to meet their short reach connectivity requirements in designs for the most advanced FinFET processes and deliver differentiated products to the market quickly.”