Synopsys, Inc. (Nasdaq: SNPS) announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform. It has been optimized to provide maximum designer productivity for designers of advanced 5G, HPC, AI and IoT applications using the Samsung 3nm GAA process technology.
Complexity at advanced nodes means designers are looking for new methods to shorten design cycles. Through close collaboration, Samsung and Synopsys provide a flow that is optimized to overcome design complexity and provide the best possible productivity for 3nm GAA design. Key features of the flow include in-design electromigration analysis, which shortens design closure time by providing accurate electromigration analysis before the layout is complete. It also includes Live design rule checking (DRC) with Synopsys’ IC Validator physical verification solution, enabling layout engineers to quickly check for design rule violations directly from the layout canvas as they work.
The AMS reference flow provides a proven methodology for designing at 3nm GAA process technology. This methodology, which has been validated by Samsung, includes a full set of documented flows and design examples. Covered topics include design entry, circuit simulation, Monte Carlo analysis, noise analysis, RF analysis, aging and EM/IR analysis, parasitic simulation, layout and signoff.
“With the Synopsys AMS Reference flow, designers can quickly deploy 3nm GAA technology for their most demanding applications, such as artificial intelligence, 5G networking, automotive, the Internet of Things and advanced data centers,” said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “The advanced methodologies enabled by Synopsys help our customers and internal IP developers to create analog and mixed-signal designs more efficiently.”
The Synopsys Custom Design Platform is based on the Custom Compiler ™ design and layout environment and includes HSPICE® circuit simulator, FineSim® circuit simulator, CustomSim™ FastSPICE circuit simulator, Custom WaveView™waveform display, StarRC™ parasitic extraction, and IC Validator physical verification. The platform features natively integrated StarRC extraction to provide early feedback of the impact of parasitics on circuit behavior, performance and pioneering visually-assisted layout automation capabilities that simplify creation of advanced-node layout.
“In developing the 3nm GAA AMS Design Reference Flow, Samsung and Synopsys worked together to enable powerful techniques for shortening design cycles,” said Aveek Sarkar, vice president of engineering at Synopsys. “As one example, the reference flow with Synopsys includes a novel solution for early electromigration analysis, which substantially shrinks design closure time.”