SIMON BUTLER, General Manager, Perforce
The CHIPS and Science Act of 2022 is perhaps the greatest boon to U.S. semiconductor manufacturing in history. This act provides $52 billion in subsidies for chip manufacturers to build fabrication plants in the U.S. For reference, currently only 12% of all semiconductor chips are made in the U.S.
This act comes amidst a global chip shortage and record inflation, with lawmakers hoping that American-made chips will solve cost and supply chain issues. In short, this is something the U.S. needs to reassert its historical influence on semiconductor manufacturing. Here we examine how businesses can use funding from the CHIPS Act to adapt, innovate, and strengthen the domestic semiconductor industry.
Focusing on improved security
One of the biggest considerations, and benefits, to domestic-made semiconductors is security. Recent geopolitical instability has caused concern over potential IP leakage and theft. For the U.S. Department of Defense (DoD), it is imperative to have a secure and trusted ecosystem for the design and manufacture of semiconductors. Design data and its implementation must be hosted privately, and updates and patches need to be delivered securely. But with most of today’s manufacturing done overseas, the DoD have had major challenges executing their national security-related projects.
The automotive industry is another area that will benefit from a trusted ecosystem and a more resilient supply chain. As we progress towards autonomous vehicles, compromised components could be used by malicious parties to take control of the system and cause damage and injury.
In these cases (and others), it’s clear that there is a need for component and IP provenance to reduce the likelihood of security breaches. More competitive and accessible domestic manufacturing can help solve this by keeping sensitive IP within the borders of the U.S.
The case for chiplets
It’s important for semiconductor companies to utilize the CHIPS Act funding as effectively as possible. One way to do this is by switching to a chiplet-based design flow. This manufacturing method implements 2.5D/3D packaging techniques and the integration of IPs as discrete dies on a common substrate. This is becoming more popular as a way of reducing respin costs (by only requiring the respin of one chiplet) and allowing chiplets based on a more cost-effective mature process node to coexist with high performance chiplets based on the latest process technology. This “cherry picking” of process nodes allows us to use the appropriate process based on the design requirement for that functional block.
Also of interest is the possibility of including dies from different foundries in the chiplet-based SoC. If we take this to its logical conclusion, then perhaps an independent entity solely focused on packaging these chiplets on an SoC could come out of the CHIPS initiative. This would enable a healthy ecosystem of larger complex foundries that can handle the aggressive process nodes and a collection of smaller fabs that can deliver the less performance-critical IPs on the SoC.
Better provenance for traceability
From the above discussion we’ve seen that one way to best leverage the CHIPS investment is to promote a healthy ecosystem with varying semiconductor manufacturing capability. One way to enable this is to embrace chiplet assembly and packaging techniques and to mix and match process nodes as required on the same SoC.
However, this introduces new concerns that must be dealt with. As mentioned, in a chiplet-based flow, we are integrating individual dies as IPs using advanced packaging techniques. This implies that the final integration is performed by the foundry (or perhaps an advanced packaging facility) that introduces a traceability requirement to ensure the versions of these chiplets are integrated reliably and without any kind of external compromising/tampering.
These chiplets are delivered to the foundries and instantiated on the final SoC with their own lifecycle and traceability concerns. Some way of tracking changes and versions using an immutable record of changes will be a necessity for these new domestic-made chiplets.
Scalable asset management will be a necessity
Another area of new complexity is the amount of data being transferred during the chiplet integration process, both for the mask data delivered to the foundries for integration and the models required by the SoC design house. A scalable asset management system will be required to handle these large datasets and deliver IPs in a secure form with a blockchain implementation (or similar) to construct the hierarchical relationships necessary for traceability in the life cycle management process. Enabling a secure, traceable ecosystem between SoC development teams, chiplet providers, and foundries is the preferred platform for this kind of design work.
What to expect going forward
In summary, will the CHIPS and Science Act solve the supply chain bottleneck plaguing the semiconductor industry? That will take some time to determine. But, with proper strategic planning, including improved provenance and scalable asset management, semiconductor companies can address other critical issues – for example the need for a single source of truth – by adopting IP lifecycle management as a core competency.