Siamak Salimy, Ph.D., Founder and CTO of Hprobe
Nearly every new technology breakthrough in the semiconductor industry targets high volume manufacturing and comes with its unique specificities. This results in challenges for engineers to manufacture and test new integrated circuits (ICs) on the wafer. To support the development of a product reaching the end user, the wafers have to be tested by addressing the uniqueness of the technology. We have seen over the past decades many wafer test challenges resolved for a number of technologies in the semiconductor industry, such as DRAM (Dynamic Random Access Memory) technology, present in all of our personal computers (PCs).
DRAM 300mm wafers are today probed entirely in a very few number of touch/down of the probes on the wafer, thanks to very advanced probe cards system. This has been instrumental in the cost reduction of DRAM and consequently cost reduction of our PCs. Other types of test challenges have been solved on the MEMS (Micro Electro Mechanical System) sensors side; these are largely present in mobile phones and cars measuring acceleration or rotation. In the deployment of MEMS technologies to volume manufacturing, it has been very challenging to test and validate the mechanical to electrical transducing performances of the sensors. Indeed, this required the devices to be moved while testing them electrically to ensure they can detect and sense the motion accurately. Hopefully, this has today been mostly overcome and we now see so many MEMS devices in our everyday lives.
More recently, we see challenges for testing and supporting the large scale deployment of 5G Silicon On Insulator (SOI) wafers substrates and related ICs products. As the 5G communication protocols is of large frequency bandwidth, it is required to probe the wafers at RF and microwave frequencies which is costly and challenging, especially with production volume performances. Also, testing the devices at power is challenging, as very high dynamics of measurements are required. Along with the 5G and the corresponding big amount of data involved at debit rates of above 10Gbps, ultra-fast CPU associated with high speed and dense memory is mandatory.
Lastly, we see an emerging spintronic memory technology on its way for large volume manufacturing. It is working by using the intrinsic magnetic orientation (spin) of electrons to store information. This is the STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) which is the most promising candidate of non-volatile embedded memory for the Internet of Things, Artificial Intelligence and a great candidate to support 5G deployment in our handset devices. STT-MRAM could also potentially replace traditional DRAM and SRAM memories thanks to its fast speed, low consumption, and scalability to very low technological nodes (below 20nm). STT-MRAM is based on the Magnetic Tunnel Junction (MTJ), which is a sandwich of two thin magnetic layers separated by a tunnel barrier interface. STT-MRAM MTJ is a bi-state device with low resistance state when the magnetic orientation of the magnetic layers is in the same direction and high resistance state when the two magnetic orientations are in the opposite direction. Each of these states belongs to one state of the bit, ‘0’ or ’1’ respectively. As it is a magnetic device, some of the physical parameters must be extracted by applying an external magnetic field above the wafer while probing it electrically. This promising spintronic memory for embedded applications is targeting very large volume deployment with its own specificity of being a magnetic device. Consequently, it is challenging to test STT-MRAM with an external magnetic field applied on top of the wafer while probing. This is especially difficult when a high throughput of wafers is required and a corresponding testing time per chip as small as possible to not impact the cost per chip. We, at Hprobe, have today resolved these challenges to support the industry towards a move to STT-MRAM in volume manufacturing.