Rambus Inc. (NASDAQ: RMBS), a provider of chips and silicon IP making data faster and safer, today announced the Rambus HBM2E memory interface subsystem, consisting of a fully-integrated PHY and controller, is silicon proven on Samsung’s advanced 14/11nm FinFET process. Leveraging over 30 years of signal integrity expertise, the Rambus solution operates up to 3.2 Gbps, delivering 410 GB/s of bandwidth. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.
“Our partnership with Rambus brings together industry-leading memory interface design expertise with Samsung’s state-of-the-art process and packaging technologies,” said Jongshin Shin, vice president of Design Platform Development at Samsung Electronics. “Designers of AI and HPC systems can implement platforms using HBM2E memory leveraging Samsung’s advanced 14/11nm process to achieve unmatched levels of performance.”
The fully-integrated, production-ready Rambus HBM2E memory subsystem runs at 3.2 Gbps and provides designers with substantial headroom for implementation. Rambus and Samsung teamed to validate the HBM2E PHY and Memory Controller IP in silicon using Samsung’s 14/11nm process and advanced packaging technologies.
“With silicon operation up to 3.2 Gbps, customers can implement HBM2E memory subsystems with the confidence of ample margin for their designs,” said Matt Jones, general manager of IP Cores at Rambus. “Our customers benefit from our comprehensive support that includes 2.5D package and interposer reference designs, helping ensure first-time-right implementations.”
