|Sony CXD5315GG in the PlaySation Vita
Inside we found the usual set of wireless chips, motion sensors, and memory, but the key to the increased performance of the PS Vita is the Sony CXD5315GG processor, a quad-core ARM Cortex-A9 device with an embedded Imagination SGX543MP4+ quad-core GPU.
Above I said that we found memory, but actually the only discrete memory that we found on the motherboard was 4 GB of Toshiba flash; and Sony’s specification states that there is 512 MB (4 Gb) regular RAM, plus 128 MB (1 Gb) VRAM (video RAM). In a phone that would tell me that there is memory in a package-on-package (PoP) configuration, mobile SDRAM in the top part and the processor in the bottom part.
However, when we took the part off the board and did a set of x-rays, the side view proved me wrong – it’s a stack, and the close-up shows that there appear to be five dies in there, a thick die at the base, a thinner one immediately on top and three smaller die on top of that. The second die down could be a spacer, since there don’t seem to bond wires going to it.
|Side x-ray images of Sony CXD5315GG
This immediately led us to speculate – if the second die up is the VRAM, is it wide I/O DRAM, and is it using through-silicon vias (TSVs)? Time for a real cross-section to check that out, and almost predictably we were disappointed:
|Sony CXD5315GG package cross-sectioned
This type of face-to-face connection showed up back in 2006 in the original Sony PSP, and Toshiba had dubbed it “semi-embedded DRAM”, now they are calling it “Stacked Chip SoC”. The ball pitch is an impressive ~45 µm, almost as tight as TI’s copper pillars, but they are staggered to achieve 40-µm pitch.
So what are the five chips that are in the stack? At the base we have the processor chip; face to face with it is a Samsung 1-Gb wide I/O SDRAM; and the top three dies comprise two Samsung 2-Gb mobile DDR2 SDRAMs, separated by a spacer die, and conventionally wire-bonded. The base die is ~250 µm thick, and the others ~100 – 120 µm.
When we look at the die photos of the processor and the 1-Gb memory, we can see that they are purposely laid out for the stacked-chip configuration, since in the centres of both is an array of matching bond pads.
|Die photos of the Sony CXD5315GG (left) and Samsung 1-Gb wide I/O SDRAM with bond pad arrays annotated
Close examination reveals that there are 1080 pads in two blocks of 540 (2 sub-blocks of 45 rows of 6 pads), so likely 2 x 512 bit I/O operation, possibly sub-divided into 4 x 128.
|Wide I/O bond pad arrays in Sony CXD5315GG (top) and Samsung SDRAM
Last year at ISSCC Samsung described a similar wide I/O DRAM using TSVs , claiming a data bandwidth of 12.8 Gb/s, four times the bandwidth of an equivalent LPDDR2 part. I doubt that the authors expected their design to be in a volume consumer device before the end of the year, but that seems to be what happened!
|Chip architecture of Samsung 1Gb Wide-I/O DRAM and SEM image of microbumps (Source: Samsung/ISSCC)
This uses similar I/Os, but not the same as, the JEDEC wide I/O standard issued earlier this year (which calls for 50 rows of 6 pads in each block), and of course it predates it by about a year.
 J-S. Kim et al., A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4Ã??128 I/Os Using TSV-Based Stacking, ISSCC 2011, pp. 496 – 498.