Tackling Design for Yield Questions at DAC

Foundries supply process information to chip designers, but according to Dr. Zhihong Liu, CEO of ProPlus Design Solutions (one of the organizers of the session), this process information is sometimes either too conservative or too optimistic, and the foundry models may be used inappropriately or incorrectly on an application-specific basis. Compounding the problem are selective corner models (i.e., process, voltage and temperature or “PVT” corners) and Monte Carlo analysis approaches often employed by circuit designers may give limited information, giving them low confidence on the yield prediction and design optimization.

The panel will look at advanced process node challenges that highlight increased random process variations and layout-dependent effects designers must address in SoC design. The panel of foundry experts will share techniques to manage these sub-nanometer effects to improve manufacturability and yield.

Liu said Monte Carloanalysis works well, but can be costly because it takes so long to run. In the past, designers have used Monte Carlo analysis for some key components, but now it will be required more often for “all kinds of circuits and components,” Liu said. He added that there are some tricks you can use to ease the pain of Monte Carlosimulation, such as parallelization and advanced algorithms. “People generally use so-called advanced sampling technology. That is a sort of statistical algorithm, trying to not reduce the accuracy of the simulation in terms of statistics, yet still significantly reduce the sampling size so that you don’t need to simulate a thousand or million of times, Liu said.

Design for Yield (DFY) has quite a different meaning to the chip design industry than Design for Manufacturing (DFM). DFM was a common buzzword in the 2004-2005 timeframe, although everyone seemed to define it a bit differently. EDA suppliers eventually came up with a commercial DFM solution, after which the term DFM fell out of favor. DFY today refers to the gap between what the designers think they need to guarantee a reliable design and what the manufacturer or foundry think they need from the designers to be able to manufacture the product in a reliable fashion.

SoCs are clearly getting bigger and more complex. At the Advanced Semiconductor Manufacturing Conference in May, Subi Kengeri, vp of advanced technology architecture at GLOBALFOUNDRIES, said 47% of SoC designs now use more than 5M gates. There are also a larger number of clock domains, which means managing multiple macros operating at different frequencies. There are also more voltage domains across the chip, with five now being the average.

Among the question the DFY DAC panel will address: How do foundries handle variability analysis? What are the conditions for tapeout? Can designers trust the foundry models? Do they need to run Monte Carlo analysis (and if so, how can they speed it up?). How many PVT corners do they need to verify?

Liu says that designers need to have support from CAD vendors, and also they need to have the model variation information from foundries. “If those are well integrated with a reasonable efficiency, the design job will be more suitable for higher yield or a better tradeoff between yield and performance,” he said. If that doesn’t exist (and it often doesn’t) bad things can happen. “Sometimes, if you do not have a way to justify a reasonable yield, the best way to make sure that you can get your tapeout success is to build in a lot of margins. That’s why the more advanced technology nodes don’t give what Moore’s Law predicted: because we have to design in a lot of margin to deal with the process variation,” Liu said. Never fear, the “secrets” will be revealed in June. I hope to see you there.