Intel 4 Process Drops Cobalt Interconnect, Goes with Tried and Tested Copper with Cobalt Liner/Cap

At the VLSI Symposia in June, Intel presented a paper “Intel 4 CMOS Technology Featuring Advanced FinFET Transistors Optimized for High Density and High-Performance Computing.” Blogger Dick James reports on details of the interconnect strategy.

CSP Market Forecast – Strong

Chip-Scale Packages (CSP) continue to be in strong demand for IC needing the smallest form-factors for applications including automotive, industrial applications to mobile phones and wearable electronics, according to leading market research firm TechSearch International. TechSearch’s latest CSP market forecast…

Nowhere Near Room Temp Superconductors

On-chip metal interconnects limit IC speed in many advanced design today, and with signal delay proportional to the product of the resistance (R) of wires and the capacitance (C) of dielectric insulation, wires with R lower than that of copper…

Bottoms-up ELD of Cobalt Plugs

As reported in more detail at Solid State Technology, during the IEEE IITC now happening in Grenoble, imec and Lam showed a new Electroless Deposition (ELD) cobalt (Co) process that is claimed to provide void-free bottoms-up pre-filling of vias and…