The promise of a new type of computer chip that could reshape the future of artificial intelligence and be more environmentally friendly is explored in a technology review paper published by UC Riverside engineers in the journal Device.
Known as wafer-scale accelerators, these massive chips made by Cerebras are built on dinner plate-sized silicon wafers, in stark contrast to traditional graphics processing units, or GPUs, which are no bigger than a postage stamp.
The peer-reviewed paper by a cross-disciplinary UCR team concludes that wafer-scale processors can deliver far more computing power with much greater energy efficiency—traits that are needed as AI models grow ever larger and more demanding.
“Wafer-scale technology represents a major leap forward,” said Mihri Ozkan, a professor of electrical and computer engineering in UCR’s Bourns College of Engineering and the paper’s lead author. “It enables AI models with trillions of parameters to run faster and more efficiently than traditional systems.”
GPUs became essential tools for AI development because they can perform many computations at once—ideal for processing images, language, and data streams in parallel. The execution of thousands of parallel operations simultaneously allows for driverless cars to interpret the world around them to avoid collisions, for images to be generated from text, and for ChatGPT to suggest dozens of meal recipes from a specific list of ingredients.
But as AI model complexity increases, even high-end GPUs are starting to hit performance and energy limits.
“AI computing isn’t just about speed anymore,” Ozkan said. “It’s about designing systems that can move massive amounts of data without overheating or consuming excessive electricity.”
The UCR analysis compares today’s standard GPU chips with wafer-scale systems like the Cerebras Wafer-Scale Engine 3 (WSE-3), which contains 4 trillion transistors and 900,000 AI-specific cores on a single wafer. Tesla’s Dojo D1, another example, includes 1.25 trillion transistors and nearly 9,000 cores per module. These systems are engineered to eliminate the performance bottlenecks that occur when data must travel between multiple smaller chips.
“By keeping everything on one wafer, you avoid the delays and power losses from chip-to-chip communication,” Ozkan said.
