By 2030, the new report “AI Chips for Data Centers and Cloud 2025-2035: Technologies, Market, Forecasts” from market intelligence firm IDTechEx forecasts that the deployment of AI data centers, commercialization of AI, and the increasing performance requirements from large AI models will perpetuate the already soaring market size of AI chips to over US$400 billion. However, the report finds that underlying technology must evolve to remain competitive with the demand for more efficient computation, lower costs, higher performance, massively scalable systems, faster inference, and domain-specific computation.
Frontier artificial intelligence (AI) has persistently attracted hundreds of billions in global investment year on year, with governments and hyperscalers racing to lead in domains like drug discovery and autonomous infrastructure.
Graphics processing units (GPUs) and other AI chips have been instrumental in driving the growth in performance of top AI systems, providing the compute needed for deep learning within data centers and cloud infrastructure. However, with the capacity of global data centers expected to reach hundreds of GWs in the coming years, and investments reaching hundreds of billions of US dollars, concerns about the energy efficiency and costs of current hardware have increasingly come into the spotlight.
The largest systems for AI are massive scale-out HPC and AI systems – these heavily implement GPUs. These tend to be hyperscaler AI data centers and supercomputers, both of which can offer exaFLOPS of performance, on-premise or over distributed networks.
High-performance GPUs have been integral for training AI models; however, they do face various limitations. These include high total cost of ownership (TCO), vendor lock-in risks, low utilization for AI-specific operations, and can be overkill for specific inference workloads. Because of this, an emerging strategy used by hyperscalers is to adopt custom AI ASICs from ASIC designers, such as Broadcom and Marvell.
These custom AI ASICs have purpose-built cores for AI workloads, are cheaper per operation, are specialized for particular systems, and offer energy-efficient inference. These also give hyperscalers and CSPs the opportunity for full-stack control and differentiation without sacrificing performance.
Both large vendors and AI chip-specific startups have released alternative AI chips, which offer benefits over the incumbent GPU technologies. These are designed using similar and novel AI chip architectures, intending to make more suitable chips for AI workloads, targeted at lowering costs and more efficient AI computations. Some large chip vendors, such as Intel, Huawei, and Qualcomm, have designed AI accelerators using heterogeneous arrays of compute units (similar to GPUs), but purpose-built to accelerate AI workloads. These offer a balance between performance, power efficiency, and flexibility for specific application domains.
AI chip-focused startups often take a different approach, deploying cutting-edge architectures and fabrication techniques with the likes of dataflow-controlled processors, wafer-scale packaging, spatial AI accelerators, processing-in-memory (PIM) technologies, and coarse-grained reconfigurable arrays (CGRAs).
The various technologies involved in designing and manufacturing give a wide breadth for future technological innovation across the semiconductor industry supply chain. Government policy and heavy investment show the prevalent interest in pushing frontier AI toward new heights, and this will require exceptional volumes of AI chips within AI data centers to meet this demand. In “AI Chips for Data Centers and Cloud 2025-2035: Technologies, Market, Forecasts“, IDTechEx forecasts that the AI Chips market will reach US$453 billion by 2030 at a CAGR of 14% between 2025 and 2030.
