Avatar Integrated Systems, a leader in next-generation physical design solutions, today announced it has added significant new features to its Aprisa™ place and route solution with the recent 19.1 rel.3 version of the product. Avatar introduced Sibling Routing™ and PowerFirst™ technologies in the Aprisa 19.1 release in 2019. Both of these innovative technologies have been designed to address the performance and capacity challenges of place and route at advanced process nodes and the demands for extreme low power and smaller silicon area at mainstream nodes.
Aprisa 19.1 rel.3 demonstrates Avatar’s dedication to helping designers overcome some of the most daunting challenges in IC design today. In addition to the technology advancements to the company’s flagship product Aprisa, Avatar has also been granted three new U.S. patents during Q1 2020. The patents cover techniques that enable place-and-route optimization based on path-based analysis.
“The 19.1 rel.3 is evidence of our continuous technology innovation and leadership in place and route technology and our dedication to helping customers and partners succeed,” said Dr. Ping-San Tzeng, CTO of Avatar Integrated Systems. “This latest release has been demonstrated on several customer advanced process nodes over the past six months, and we will continue to work with our customers to ensure their design success.”
In a recent Deep Chip post, users shared their experiences using Avatar’s advanced place-and-route solutions and commented that the tool is 100% successful at 7 nm.
