Cadence Design Systems, Inc. today announced a collaboration with Arm to deliver a chiplet-based reference design and software development platform to accelerate software-defined vehicle (SDV) innovation. The automotive reference design, initially for advanced driver assistance system (ADAS) applications, specifies a scalable chiplet architecture and interface interoperability to foster industry-wide collaboration, enable heterogeneous integration and expand system innovation.
The solution is architected and built using the latest generation of Arm® Automotive Enhanced technologies and Cadence® IP. The complementary software stack development platform is provided as a digital twin of the hardware that is compliant with the Scalable Open Architecture for Embedded Edge (SOAFEE) initiative software standard, enabling software development to begin before hardware is available and allowing subsequent system integration validation. The combined solution speeds both hardware and software development, accelerating time-to-market.
The growing prevalence of ADAS and SDVs is driving the need for more complex AI and software capabilities, as well as greater levels of interoperability and collaboration in the automotive electronics ecosystem. Coupled with the need to quickly customize 3D-IC systems for a plethora of automotive applications, chiplets are an increasingly attractive solution. However, it’s crucial that chiplets from different IP providers work together seamlessly. In addition, the rapid pace of automotive development necessitates that 3D-IC system developers have a software development platform to shift left in the process flow while the IP and chiplets are still being designed.
The new solution architecture and reference design provide a standard for chiplet interface interoperability, addressing a critical industry need. The Cadence components of the solution include:
- Helium™ Virtual and Hybrid Studio for the rapid creation of virtual and hybrid platforms and Helium Software Digital Twin to support deployment at scale for software developers
- I/O IP solutions for industry-leading interface and memory protocols, including Universal Chiplet Interconnect Express™ (UCIe™) for high-speed chiplet-to-chiplet communication
- Comprehensive compute IP portfolio including advanced AI solution, the Neo™ neural processing unit (NPU) IP, the NeuroWeave™ software development kit (SDK) for machine learning (ML) solutions, and world-class DSP compute solutions
“The automotive industry is evolving rapidly and AI and software advancements are emphasizing a greater need to speed up development cycles,” said Dipti Vachani, senior vice president and general manager, Automotive Line of Business, Arm. “Together with critical ecosystem partners like Cadence, we’re enabling faster software and hardware development by bringing together a complete solution of design and verification technologies underpinned by the latest Automotive Enhanced technologies from Arm, allowing developers to start building for next-generation SDVs well before silicon is available in the market.”
“Reducing the overall system design workload and shifting hardware and software development left are both crucial to meet shrinking time-to-market windows when developing today’s increasingly complex SDVs. Virtual platforms and chiplets are both key enablers for automotive 3D-IC SoC developers,” said Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence. “Working closely with Arm, we are addressing key inefficiencies in both software and hardware development and verification processes, while catalyzing the multi-die chiplet ecosystem for automotive semiconductors.”
