OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure, and trusted integrated circuits, will showcase its verification expertise of RISC-V processor cores at the upcoming RISC-V Summit being held December 10-12, 2019 at the San Jose Convention Center.
OneSpin will host attendees at both its booth and a demo pod in the OpenHW pavilion at the RISC-V Summit, while the company’s experts will present two sessions on verifying RISC-V SoCs:
Pre-Silicon Detection of Hardware Trojans and Security Vulnerabilities in RISC-V Cores
WEDNESDAY December 11, 11:30 AM – 12:30 PM, Poster Gallery on Exhibit Floor
Speaker: Sven Beyer, Product Manager Design Verification, will present a poster titled “Pre-Silicon Detection of Hardware Trojans and Security Vulnerabilities in RISC-V Cores,” co-authored by Blake Buschur of Edaptive.
More than the Core: Verifying RISC-V SoCs
WEDNESDAY December 11, 2:50 PM – 3:10 PM, Grand Ballroom 220-C
Speaker: Nicolae Tusinschi, Product Specialist Design Verification, OneSpin Solutions
Verifying RISC-V designs is critical for technical and commercial success. Compliance to the standard specifications and complete interoperability are essential to compete with older processor families with decades of proven silicon. Nicolae will describe how RISC-V processor designers, whether in-house or core providers, must apply the most rigorous verification methodologies and document this process to build the confidence of potential integrators.
For more information on how OneSpin can help with RISC-V verification, download the white paper “Assuring the Integrity of RISC-V Cores and SoCs.”
