Primarius Technologies today announced that its NanoSpice universal parallel SPICE simulator has been validated and certified for Samsung Foundry’s 3/4nm technology. NanoSpice helps Samsung Foundry’s customers to achieve precision accuracy.
Samsung’s 3/4nm process technology is engineered to improve overall yield, reduce power consumption and improve performance over previous process nodes, which requires fast and accurate circuit simulation and verification tools to support advanced IC designs. Verified under Samsung Foundry’s EDA certification program in this process technology, NanoSpice™ provides stable convergence for analog IPs, large capacitance with large netlist including post-layout information which help Samsung Foundry’s customers to design with full confidence, shortening design cycle while achieving the highest accuracy.
As a breaking generation high-capacity, high-performance parallel SPICE simulator, NanoSpice is designed for the most challenging simulation jobs, such as large post-layout analog circuit simulations that require high capacity, speed and accuracy all at the same time. Its superior parallelization technologies enable efficient circuit simulation up to 50 million circuit elements.
“Samsung and Primarius together have achieved success with NanoSpice certification at Samsung Foundry’s 3/4nm process. This collaborative partnership allows both companies to deliver the competency required to verify advanced and innovative IC designs to help drive the rapidly growing IC markets and applications,” said Sangyun Kim, Vice President and head of Foundry Design Technology Team at Samsung Electronics.
“Samsung has been a long-term customer of our EDA products and solutions, and we continue to advance our technology to cope with the simulation challenges ahead with cutting edge technologies.” remarked by Dr. Lianfeng Yang, President of Primarius. “We embrace the opportunity to be the part of the ecosystem supporting these critical process nodes, NanoSpice build with performance and accuracy to solve the toughest design verification problems with its full range of simulation capacities from small blocks to full chip designs and can help achieve goals that would be difficult to reach without our circuit simulation solutions.”
