Silicon Topology, a Taiwan-based ASIC/SoC physical layout design service provider, today announced that it has joined the Design Center Alliance (DCA) of TSMC’s Open Innovation Platform (OIP). Silicon Topology specializes in analog, mixed-signal, memories, and RF circuit layout services and is experienced with TSMC’s industry-leading process technologies, including 7nm, 5nm, 4nm, and 3nm technologies, as well as TSMC’s specialty technologies.
Focusing on ASIC physical layout services for over 25 years, Silicon Topology has accumulated comprehensive experience in many different areas, from high-speed interface IPs such as SerDes, DDR PHY to RF Tx/Rx, high precision ADC, low power oscillator, power management IC, drivers IC, and various memory design applications. The company has 200 layout experts located in support service centers in Taiwan, San Jose, Tokyo, and Nanjing to serve global customers more effectively with local resources.
“Silicon Topology has joined our Design Center Alliance to address the growing demand for high-quality chip designs using TSMC’s industry-leading technologies,” said Suk Lee, Vice President of the Design Infrastructure Management Division at TSMC. “As a valuable ecosystem partner, Silicon Topology has helped our mutual customers with its extensive IC layout services and expertise that enabled them to launch their differentiated products quickly to the market.”
“Thanks to the long-term cooperation with TSMC, Silicon Topology has been continuously enhancing our layout capabilities and resources to support TSMC’s industry-leading technologies,” said Sean Lin, CEO of Silicon Topology. “We are proud to join TSMC’s Design Center Alliance to provide our mutual customers with professional, value-added layout services to speed up the time-to-market of their products.”
