SmartDV™ Technologies is the first vendor to deliver Design and Verification intellectual property (IP) supporting the MIPI RF Front End Control Interface (MIPI RFFE) v3.0 specification, shipping it as the MIPI Alliance announced availability.
The SmartDV MIPI RFFE v3.0 protocol portfolio of Design and Verification IP includes simulation IP, assertion IP, post-silicon validation IP and SystemC models, along with RFFE master and slave Design IP. Also part of the portfolio is SimXL™, Synthesizable Transactors for accelerating system-level, system-on-chip (SoC) testing on hardware emulators or field programmable gate array (FPGA) prototyping platforms. In addition to fast porting of simulation tests to emulators and FPGA platforms, SimXL enables early software development on an FPGA platform.
“The new MIPI RFFE 3.0 specification will enable the advance of 5G, a growth opportunity our user community is following quite closely,” says Deepak Kumar Tala, SmartDV’s managing director. “It is critical to us to quickly deliver high-quality Design and Verification IP to meet our users’ exacting needs that match the features and benefits of MIPI RFFE v3.0. That’s why SmartDV continues to be the Proven and Trusted IP vendor.”
A de facto standard interface for control of radio frequency (RF) front-end (FE) subsystems, the new MIPI RFFE v3.0 protocol is designed for tight timing precision and low latencies needed to support 5G. It includes a two-wire interface to control RF subsystems for amplifiers, tuners, switches and filters and enhanced triggering and functionality including timed, mappable and extended triggers.
