At its annual Synopsys Users Group (SNUG) Silicon Valley Conference, Synopsys, Inc. (Nasdaq: SNPS) today launched Synopsys.ai, a suite of AI-driven solutions for the design, verification, testing and manufacturing of the most advanced digital and analog chips. For the first time, engineers can now use AI at every stage of chip design, from system architecture to design and manufacturing, and access the solutions in the cloud. Renesas, a leader in the automotive space, is already using Synopsys.ai to shave weeks off product development times with enhanced silicon performance and cost reduction.
The Synopsys.ai EDA suite includes AI-driven solutions:
- Digital design space optimization to achieve power, performance and area (PPA) targets, and boost productivity (used in 100 production tape-outs by January 2023).
- Analog design automation for rapid migration of analog designs across process nodes.
- Verification coverage closure and regression analysis for faster functional testing closure, higher coverage and predictive bug detection.
- Automated test generation resulting in fewer, optimized test patterns for silicon defect coverage and faster time to results.
- Manufacturing solutions to accelerate development of lithography models with high accuracy to achieve the highest yield.
“Increased complexity, engineering resource constraints and tighter delivery windows were challenges crying out for a full AI-driven EDA software stack from architectural exploration to design and manufacturing – and we’ve delivered it,” said Shankar Krishnamoorthy, GM of Synopsys EDA Group. “With Synopsys.ai solutions, our customers’ ability to search design solution spaces across multiple domains is in hyperdrive. They’re finding optimal results far faster as the .ai learns run-to-run, and it’s transforming their ability to meet and beat tough design and productivity targets.”
