Addressing complex customer requirements for heterogeneous compute-intensive applications, Synopsys, Inc. today announced the availability of the industry’s most comprehensive EDA and IP solutions for 2D/2.5D/3D multi-die systems for TSMC’s most advanced N7, N5 and N3 process technologies. In collaboration with TSMC on its 3DFabric technologies and 3Dblox standard, Synopsys provides a holistic, system-level approach with production-proven solutions that enables mutual customers to meet the stringent power and performance requirements for complex multi-die systems.
“Synopsys’ achievements in multi-die system design technologies complements TSMC’s advanced packaging and silicon process technologies in this area, providing our mutual customers with a comprehensive solution for further semiconductor and system-level innovation,” said Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC. “Together, we are leading the way with differentiated design solutions that will bring to life new applications in AI, high-performance computing, networking, mobile and other key areas.”
Key drivers such as cost-effective integration, optimized system cost and performance, lower total power and faster time-to-market are accelerating the shift to multi-die system designs. Compared to their monolithic counterparts, multi-die systems feature a myriad of interdependencies and must be approached holistically from a system perspective. Synopsys EDA tools and IP address all aspects of multi-die systems from architectural partitioning, through silicon/package co-design, to thermal and power management, implementation, verification, software validation, system signoff and silicon lifecycle management.
A key component of the Synopsys solution is the tapeout-proven Synopsys 3DIC Compiler, a unified multi-die co-design and analysis platform that seamlessly integrates with TSMC 3Dblox and TSMC 3DFabric technologies for 3D system integration, advanced packaging and a complete exploration-to-signoff implementation. With 3DIC Compiler, design teams can efficiently bring together dies designed via Synopsys digital and custom design flows certified for TSMC N4P and N3E advanced processes. A broad portfolio of Synopsys IP, including UCIe and HBM3 IP on TSMC’s most advanced process technologies, provide high bandwidth and low-power connectivity for multi-die systems.
“Whether it’s the high level of integration in heterogeneous compute applications or the challenges of scale and systemic complexities, multi-die systems have emerged as a path forward to enable the next level of system functionality,” said Sanjay Bali, vice president of Marketing and Strategy for the EDA Group at Synopsys. “By collaborating closely with TSMC, we are providing the industry’s most comprehensive, scalable and trusted EDA and IP solutions that enable designers to accelerate system integration with reduced risk.”
