Verific Design Automation today announced long-time customer vSync Circuits added Verific’s static elaboration to its product mix and introduced vLinter, early rule-based design analysis and verification software.
“Our relationship with Verific is one of great mutual admiration,” remarks Dr. Reuven Dobkin, chief executive officer and chief technology officer of vSync. “We respect Verific and value it as a trusted vendor with incomparable support and service.”
vLinter, static analysis-based verification used in early design stages, hunts design bugs due to bad coding practices, including unsynthesizable code, unintentional latches, undriven signals, race conditions, out-of-range indexing, incomplete case statements and simulation and synthesis mismatches. It supports both ASIC and FPGA design flows and allows easy and fast setup by directly loading project files from leading synthesis software.
“VSync takes a clever approach to functional verification using structural and formal verification, RTL and gate-level verification, automatic timing constraints generation and automatic bug fixing,” remarks Michiel Ligthart, Verific’s president and chief operating officer. “The result is a powerful methodology that works in either FPGA or ASIC verification and integration flows with Verific’s parser platforms serving as the front end.”
Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are in production and development flows at semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compiles on all 32- and 64-bit Unix, Linux, Mac OS and Windows operating systems.