IBM likes to create a stir once in awhile, and judging by the tech-press response in the last week or three, they have achieved that goal with their announcement of 2-nanometer CMOS technology, developed at their Albany research centre. This technology is expected to give a 45% performance boost or 75% power reduction, compared with a 7-nm process. Of course the question is, compared with what 7-nm process?
Fan-out package revenue is expected to surpass $2B by 2025 and fan-in WLCSP revenue to peak to $3B by 2025 as TSMC continues to drive the fan-out market in 5G applications.
Innovation in memory technology is constant. In this article, TechInsights’ Jeongdong Choe reviews the latest developments in DRAM, NAND, and emerging technology, and provide insight on the trends in this space.
Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint.