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High cost per wafer, long design cycles may delay 20nm and beyond

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Comments (7)
  1. Jan Hoppe says:

    I agree with 95% of Mr. Handel’s analysis.
    But I do not know why all analysts forget ant FD SOI technology which gives less problems than 3-D Fin-Fet. It is more planar and gives a lot of advantages like smaller leakage, power voltage, easier designs and more control over yield.
    Samsung, IBM, and Global Foundries are ahead of the others on that.
    I certainly do not believe in Altera 10 nm FPGAs. First Intel must master their 14 nm yield and next 10 nm (hard to say what lithography they will use)and next Altera, a small Intel customer can benefit.

  2. I agree 100%.

    Finally, someone who isn’t connected to Intel is telling it how it really is. Forward a copy of this to David Nenni – he’ll argue all day with you.

  3. Finally, someone not connected to Intel tells it like it is.

    Send a copy to David Nenni. He’ll ague all day with you.

    1. Arnold,
      Dan Nenni’s SemiWiki also posted a near identical story. You won’t find a direct argument from him.
      https://www.semiwiki.com/forum/content/3084-handel-jones-predicts-process-roadmap-slips.html

  4. MS says:

    Intel is having problems with double patterning, not with FinFETs. As with the 32/28nm gate width node, Intel hasn’t used double patterning at 22nm gate width and has used 80nm first metal pitch, and is having difficulty with double patterning and 64nm first metal pitch which is required at 14nm gate width. TMSC has mastered double patterning, 64nm first metal pitch and now FinFET at 20nm gate width, and is transitioning to 16nm. FinFET seems to be by far the easier to master, and TMSC is reporting that it is ahead of programmed for 16nm volume SoC production in Q4 2014, and TMSC will be supplying Apple with 64bit 16nm FinFET SoCs for the Apple iPhone 6 in volume in Q1 2015. Intel looks it will start producing CPU chips (not SoCs) in volume about the same time.

    With regard to long design cycles – yes, the design rules for double patterning makes the design of 14/16nm chips far more tedious than at 32/28nm or 22nm. However this will not stop the flagship designs from volume production in Q1 2015 – it will just mean that the ramp-up across the industry will take some time, and 32/28nm and 22nm chips will coexist for some time because of the higher cost of double patterning.

  5. Technology Novice says:

    Eventual winners will be TSMC and Samsung, and then Samsung eventually. I wouldn’t be surprised if Samsung stands atop alone come 2022. TSMC has had so much trouble with its 28nm in the beginning and that has the case since then down to its 16FF. Samsung’s 28nm is rock solid as proven in A7 chips. Samsung has recruited a lot of talents of late and, trust me, what you have seen in memory space will play out exactly on logic front as well.

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