Apple Corp. recent purchased an old 200mm-diameter silicon wafer fab in San Jose capable of creating as small as 90nm device features. Formerly owned and operated by Maxim, the US$18.2M purchase reportedly includes nearly 200 working fab tools. Some people outside the industry have speculated that Apple might use this fab to do R&D on the A10 or other advanced logic chips, but this old tool-set is completely incapable of working on <45nm device features so it’s useless for logic R&D.
As reported at EETimes, this old fab could be used for the R&D of “mixed-signal devices, MEMS and image sensors and for work on packaging.” Those who know do not speak, while those who speak do not know…I do not know so I’m free to join the public speculation. Mixed-signal and MEMS processing would require major re-tooling of the line, but this 15-20 year-old tool-set is nearly turn-key for wafer-level packaging (WLP). With minimal re-tooling, this line could produce through-silicon vias (TSV) or through-mold vias (TMV) as part of Fan-Out WLP (FO-WLP).
Our friends at ChipWorks have published a detailed tear-down analysis of the System-in-Package (SiP) used in the first generation Apple Watch; it contains 30 ICs and many discretes connected by a 4-layer printed circuit board (PCB). Significant power and performance improvements in mobile devices derive from stacking chips in such dense packages, and even greater improvements can found in replacing the PCB with a silicon interposer. With Apple pushing the limits on integrating new functionalities into all manner of mobile devices, it would be strategic to invest in WLP R&D in support of application-specific SiP design.